Processor-based systems rely on memory devices to store data so that the processor can access and manipulate the data. Memory devices include non-volatile media, such as read-only memory (ROM), hard disk drives and compact disk (CD) ROM drives, as well as volatile media, known as random access memory (RAM). The RAM is directly accessible by the processor. Thus, data stored on the hard disk drive is loaded into RAM before processing can begin.
A processor-based system, such as a personal computer, may include more than one type of RAM. Dynamic RAM, or DRAM, is typically used as the computer's main memory because of its low cost and high density (i.e., megabits per chip). Each cell in a DRAM includes a single transistor and a capacitor for storing the cell state (either a “1” value or a “0” value). The DRAM cells must be refreshed periodically in order to maintain the cell state.
Static RAM, or SRAM, stores data in a flip-flop. SRAM cells usually include four to six transistors. Because SRAM cells need not be refreshed, they operate at faster speeds than DRAM cells. However, SRAM cells take up more space and are more expensive. SRAM cells are typically used for level-one and level-two caches within the processor-based system.
High-performance very large scale integration (VLSI) systems employ large amounts of on-die SRAM for the cache function. As scaling of such technologies continues, particular attention is given to the performance of the SRAM as well as its die size. Since the SRAM cell supports both read and write operations, its performance is measured by its read stability and its write margin. The performance criteria coupled with the need to maintain a small cell area are particularly challenging for any new SRAM design.
The read stability and the write margin make conflicting demands on the SRAM cell. During a read operation, the SRAM cell preferably has “weak disturbance” at the internal storage nodes in order to avoid being erroneously flipped (from a “1” state to a “0” state, and vice-versa). This is preferred whether a “true read,” in which the contents of the cell are sent to read/write circuitry, or a so-called “dummy read,” in which the read is not actually processed, takes place. During a write operation, the SRAM cell preferably has “strong disturbance” in order to successfully flip the cell. Thus, read stability depends on weak disturbance within the SRAM cell while write margin depends on strong disturbance within the same SRAM cell.
The apparent paradox between read and write requirements has made SRAM cell scaling extremely difficult. For the current generation of SRAM memory, cell scaling is limited by both the read and write operations. Thus, future implementations of SRAM memories, using the current technology, are not expected to show improvements in read stability and write margin, nor are cell sizes expected to be made smaller, due to the conflicting performance requirements of reads and writes.
Thus, there is a continuing need to design an SRAM memory cell that meets both the read stability and the write margin requirements, while a minimum cell area is maintained.